PURPOSE: To reduce the cost of a device by releasing a phase locked loop circuit from being locked at the 1st frequency F 1 with a signal of the 2nd frequency F 2 close to the 1st frequency F 1 when there is a signal of specific frequency which needs to be detected.
CONSTITUTION: When the signal GS which needs to be detected appears, a BPF 9 generates a signal G 2 with the high frequency part of the signal GS, and this signal is amplified 10 and converted into a pulse signal G 2 ' of repetitive frequency F 2 . When the signal G 2 ' is applied to an addition point 12, the PLL circuit 6 is led in at the frequency F 2 and unlocked from the frequency F 1 , so that the state is decided by a comparator 18. The signal GS, on the other hand, is detected from a background noise GN through an amplifier 19 and a BPF 20 and the signal GS is applied to the PLL circuit 21, so the locking state of the frequency FS is decided by a comparator 23. Then, the output of the comparator 18 is ivnerted by inverter 24 and inputted to an AND gate 25 along with the output of the comparator 23 to check the coincidence of the signal GS with the circuit 6 and 21, thereby deciding whether there is the signal GS or not with the output of the gate 25.